Electrolyte-Gated Oxide Electronics

Inkjet-printed electrolyte-gated transistors (EGTs) combine solution-deposited oxides with printable electrolytes, enabling microelectronic circuits below 1 V on various substrates.

Device architecture. Each transistor is built up in four layers on glass, polymer substrate, or PET substrates. Indium tin oxide (ITO) source and drain electrodes define the channel gap. An indium oxide (In₂O₃) semiconductor film is inkjet-printed across that gap to form a crystalline channel. A composite solid polymer electrolyte (CSPE) or ion-gel is then printed on top, covering the channel. Finally, a PEDOT:PSS top-gate electrode is printed onto the electrolyte surface. The result is a bottom-contact, top-gate device in which every active layer is solution-deposited. When a voltage is applied to the gate, mobile ions in the electrolyte redistribute and form an electric double layer (EDL) directly at the semiconductor surface, with a capacitance density of around 3 to 5 µF/cm², a hundred to a thousand times higher than thermally grown oxide dielectrics of comparable thickness. That is why the devices switch fully at gate voltages below 1 V.

Indium oxide as the channel material. We print our transistor channels from In₂O₃, a wide-bandgap n-type oxide semiconductor deposited by inkjet from a nitrate precursor ink. After annealing at 300 to 350 °C, the channel develops an electron mobility that intrinsically exceeds 100 cm²/Vs. In practice, our transistors show threshold voltages around 0.1 V, on/off exceeding 10⁶, and subthreshold swings around 100 mV/decade. We have also developed gallium-doped indium oxide (IGO) nanoparticle inks as an alternative route that enables threshold voltage tuning by changing dopant concentration and reducing process temperatures down to 100 °C.

From device to design kit. One of the most distinctive features of our research is the commitment to building the complete design infrastructure around each process we develop, mirroring the methodology of mature silicon IC design. For our EGT platform this means: an EKV-based SPICE compact model, calibrated against 88 individually measured transistors across multiple fabrication runs; a full process design kit (PDK) with parametric device cells, standard cells for digital logic, layout design rules, and DRC scripts. A non-quasi-static Meyer capacitance model extended specifically for electrolyte-gated devices, essential for accurately simulating circuits, is also integrated into the PDK. This infrastructure means that a new circuit can be designed, simulated, and laid out before a single drop of ink is dispensed, dramatically shortening the iteration cycle.

Extending to flexible substrates. On PI, fully printed inverter circuits incorporating graphene passive electrodes achieved a signal gain of 3.5, a result that required careful optimisation of the graphene ink formulation, the substrate surface treatment, and the encapsulation scheme. We have also demonstrated a 3D polymer reservoir EGT architecture in which a laser-written microchannel (90 x 90 µm cross-section) serves as the electrolyte reservoir, with platinum inner electrodes, enabling precise volume control and opening a path toward biosensor applications.

Circuit demonstrations. The true test of a transistor technology is what it enables at the circuit level, and here our group has steadily pushed the complexity frontier. Starting from individual devices, we built three-stage ring oscillators that operate from a minimum supply of 0.6 V and reach 352 Hz at 2 V, benchmarks that define the practical speed envelope for our current process. We then demonstrated a static random-access SR latch with rail-to-rail output swings at 1 V, pass-transistor logic gates that reduce transistor count dramatically compared to standard complementary designs (our XNOR gate uses two transistors rather than the usual eight), and complementary-style logic using depletion-mode EGTs as pseudo-p-type surrogates, a workaround for the absence of a printed p-type oxide semiconductor with sufficient performance. A hardware security primitive, a physical unclonable function (PUF) exploiting process variation between nominally identical transistors, demonstrated near-ideal inter-device uniqueness of 50.1% and reliability of 89%, validating the viability of our platform for printed hardware security applications.

Cross-pillar integration. Our design methodology is not confined to oxide n-type EGTs. We have adapted the PDK approach to organic p-type thin-film transistors (OFETs) within a flexible hybrid organic PDK (FH-OPDK), and used it to design and fabricate a 16 x 16 active-matrix pressure sensor combined with a 4 x 16 binary decoder on a flexible substrate. This result demonstrates that the design-kit methodology scales across material systems and validates organic and oxide printed electronics. Looking further toward memory-integrated electronics, we are working on combining our EGT as a selector element with a printed resistive memory (memristor) in a 1-transistor-1-resistor (1T1R) cell architecture. Such a cell is the fundamental building block of resistive crossbar arrays for in-memory and neuromorphic computing; realising it in fully printed form would bridge our transistor and memristive device research and open a new application space for printed electronics.

Further information:

Cross-Section EGT — Electrolyte-gate field-effect transistor (EGT)

Ring Oscillator — Ring oscillator based on EGTs and resistors

Ringo Measurement — Ringoscillator measurement

Preasure sensor — Active-maxtrix pressure sensor with binary deocder